The present invention relates to an arithmetic logic unit of a stored program sequence controller which stores a program equivalent to a relay sequence in a program memory and carries out sequence control in accordance with the stored program.
A conventional arithmetic logic unit of the sequence controller of this type includes a result memory and arithmetically or logically processes signals from a signal input device and a signal output device and signals stored in the result memory in accordance with the program stored in the program memory.
FIG. 1 shows an example of the conventional sequence controller in which PM denotes a program memory, I/O denotes a signal input/output device and ALU denotes an arithmetic logic unit. The program memory stores a program equivalent to a relay sequence. The program consists of an aggregation of instructions each comprising an operation code field OP indicating a type of instruction INS and an operand field OR for specifying signals to be processed by the instruction, as shown in FIG. 2. The program memory PM sequentially and cyclically reads out the instructions stored therein. The operation code field OP of the read instruction is fed to the arithmetic logic unit ALU through an instruction signal line 6, and the operand field OR is fed to the signal input/output device I/O through an input/output select signal line 7. The signal input/output device I/O may be connected to an equipment for detecting status of a process which controls the sequence controller, such as limit switches, and connected to a process equipment which the sequence controller controls, such as solenoid switches or solenoid valves. The signal input/output device I/O receives the operand field OR, selects the input/output signals to be processed and supplies the selected input/output signals to the arithmetic logic unit ALU through an input/output read signal line 10 in accordance with timing of an input/output control signal which is supplied from the arithmetic logic unit ALU through an input/output control signal line 13. The arithmetic logic unit ALU comprises an arithmetic logic circuit 1, an accumulator 2 and a result storing register 3 and the arithmetic logic circuit 1 carries out predetermined arithmetic and logic operations on the signals supplied from the accumulator 2, the signal input/output device I/O and the result storing register 3 in accordance with the operation code OP supplied through the instruction signal line 6. Upon the end of the arithmetic and logic operations, the arithmetic logic circuit 1 issues a stepping signal to the program memory PM through a stepping signal line 8 to read out the next instruction. The arithmetic logic circuit 1 then again carries out the arithmetic and logic operations in accordance with the operation field OP of the instruction. The above operation is repeated to carry out the control process.
FIG. 3 shows an example of a relay sequence, in which A, B, C, D and E denote contacts and F denotes a relay coil. A prior art sequence controller is explained in detail with reference to FIG. 3. The relay sequence is converted to a program by aggregation of instructions LOD, AND, OR, AND STR, OR STR and OUT, and the program thus constructed is stored in the program memory PM. The operations of the arithmetic logic unit ALU for the respective instructions are shown below.
LOD instruction: Store the content of the accumulator 2 in the result storing register 3 and read the signal from the signal input/output device I/O into the accumulator 2. PA0 AND instruction: AND the content of the accumulator 2 with the signal from the signal input/output device I/O and load the result in the accumulator 2. PA0 OR instruction: OR the content of the accumulator 2 with the signal from the signal input/output device I/O and load the result in the accumulator 2. PA0 AND STR instruction: AND the content of the accumulator 2 with the signal from the result storing register 3 and load the result in the accumulator 2. PA0 OR STR instruction: OR the content of the accumulator 2 with the signal from the result storing register 3 and load the result in the accumulator 2. PA0 OUT instruction: Output the content of the accumulator 2 to the signal input/output device I/O.
With these instructions, the relay sequence shown in FIG. 3 is converted to the program shown in FIG. 4. For the sake of convenience of the explanation, step numbers are shown on the right hand. Referring to FIG. 4, when the step 1 instruction is read out of the program memory PM, "LOD" in the operation code field is applied to the arithmetic logic circuit 1 through the instruction signal line 6. The signal input/output device I/O selects "A" in the operand field through the input/output selection signal line 7 and produces a logical status signal for the input/output signal A. The arithmetic logic circuit 1 stores the output from the accumulator 2 in the result storing register 3 through an accumulator output signal line 9. The result storing register 3 is a bilaterally shiftable push down register having a common signal input and output port. A signal is stored while shifting the content of the result storing register 3 by a shift signal applied through a shift signal line 12. The content of the accumulator 2 is stored in the result storing register 3 and the signal A selected by "A" in the operand field supplied from the signal input/output device 4 (which signal A is the logical status signal "1" or "0" corresponding to ON or OFF state of the contact A selected by "A" in the operand field and is expressed in this manner for the sake of convenience of explanation. Similar expessions are used for the other signals) is read into and stored in the accumulator 2. In the step 2, the signal A stored in the accumulator 2 is stored in the result storing register 3 and a newly selected signal B is stored in the accumulator 2. In the step 3, the signal stored in the accumulator 2 and a signal C selected by the signal input/output device I/O are logically ANDed and the result is stored in the accumulator 2. In the step 4, the content of the accumulator 2 is stored in the result storing register 3 and a signal D is stored in the accumulator 2. In the step 5, the signal D stored in the accumulator 2 and a signal E selected by the signal input/output device I/O are logically ANDed and the result is stored in the accumulator 2. In the step 6, the signal last stored in the result storing register 3 is supplied to the arithmetic logic circuit 1 from the result storing register 3 through a read signal line 11. The signal supplied is a logical AND function of the signals B and C. This signal is logically ANDed with the content of the accumulator 2 and the result is stored in the accumulator 2. As the data stored in the result storing register 3 is read out, the content of the result storing register 3 is shifted in opposite direction to the store operation. In the step 7, the signal A is at the position in the result storing register 3 which is closest to the output end by the shift operation in the previous step 6. The signal A from the result storing register 3 is supplied to the arithmetic logic circuit 1 through the read signal line 11. A logical function of the signal A and the content of the accumulator 2 is stored in the accumulator 2. In the step 8, the content of the accumulator 2 is outputted at the position in the signal input/output device I/O selected by "F" of the operand field.
In this manner, the relay sequence shown in FIG. 3 is converted to the program shown in FIG. 4 which is equivalent to the relay sequence.
In the prior art unit thus constructed, if a programmer does not fully understand that the LOD instruction stores the result in the result storing register 3, the AND STR instruction and the OR STR instruction read out the content of the result storing register to use it in the operation and other instructions execute the respective operations, the programmer cannot program the instruction sequence. In addition, in order to understand those, the programmer is required to be aware of the internal construction of the sequence controller to a certain extent. As is apparent from the comparison of FIGS. 3 and 4, the expression of the instructions and the symbols of the instruction sequence do not correspond one to one but the expression of the instruction is in alphabetical language form so that the relay sequence of FIG. 3 must be rewritten into the program in the form of language as shown in FIG. 4. As a result, in the prior art unit, the programmer must be knowledgable to a considerable extent and a large number of steps are required to program the relay sequence.
When the relay sequence of FIG. 3 is to be constructed from the language program as shown in FIG. 4 by a reverse conversion process, the operator encounters a big difficulty because the symbols of the relay sequence and the language instructions do not correspond one to one.
Accordingly, keys K.sub.1, K.sub.2, K.sub.3, . . . K.sub.9 having keytops marked with elements of the relay sequence as shown in FIG. 5 are provided on a programming panel so that a relay sequence as shown in FIG. 6 can be programmed by keying those keys. In this manner, the expression of the instructions and the symbols of the relay sequence are related one to one to overcome the above difficulty.